SOURCE=0, ENBL=0, TRIG=0
Channel Configuration register
| SOURCE | DMA Channel Source (Slot) 0 (0): Disable_Signal 2 (2): UART0_Rx_Signal 3 (3): UART0_Tx_Signal 4 (4): UART1_Rx_Signal 5 (5): UART1_Tx_Signal 6 (6): UART2_Rx_Signal 7 (7): UART2_Tx_Signal 8 (8): UART3_Rx_Signal 9 (9): UART3_Tx_Signal 16 (16): SPI0_Rx_Signal 17 (17): SPI0_Tx_Signal 18 (18): SPI1_Rx_Signal 19 (19): SPI1_Tx_Signal 22 (22): I2C0_Signal 23 (23): I2C1_Signal 24 (24): TMR0_Channel0_Signal 25 (25): TMR0_Channel1_Signal 26 (26): TMR0_Channel2_Signal 27 (27): TMR0_Channel3_Signal 28 (28): XBAR_Request0_Signal 29 (29): XBAR_Request1_Signal 30 (30): XBAR_Request2_Signal 31 (31): XBAR_Request3_Signal 32 (32): AFE_Channel0_Signal 33 (33): AFE_Channel1_Signal 34 (34): AFE_Channel2_Signal 35 (35): AFE_Channel3_Signal 36 (36): Port_J_Signal 37 (37): Port_K_Signal 38 (38): Port_L_Signal 39 (39): Port_M_Signal 40 (40): SarADC_Signal 42 (42): CMP0_Signal 43 (43): CMP1_Signal 44 (44): CMP2_Signal 47 (47): MMAU_Signal 48 (48): PDB0_Signal 49 (49): PORT_A_Signal 50 (50): PORT_B_Signal 51 (51): PORT_C_Signal 52 (52): PORT_D_Signal 53 (53): PORT_E_Signal 54 (54): PORT_F_Signal 55 (55): PORT_G_Signal 56 (56): PORT_H_Signal 57 (57): PORT_I_Signal 58 (58): LPUART0_Rx_Signal 59 (59): LPUART0_Tx_Signal 60 (60): AlwaysOn60_Signal 61 (61): AlwaysOn61_Signal 62 (62): AlwaysOn62_Signal 63 (63): AlwaysOn63_Signal |
| TRIG | DMA Channel Trigger Enable 0 (0): Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 1 (1): Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. |
| ENBL | DMA Channel Enable 0 (0): DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 1 (1): DMA channel is enabled |